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general description the ds17285, ds17485, ds17885, ds17287, ds17487, and ds17887 real-time clocks (rtcs) are designed to be successors to the industry-standard ds12885 and ds12887. the ds17285, ds17485, and ds17885 (here - after referred to as the ds17x85) provide a real-time clock/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a program - mable square wave, and 114 bytes of battery-backed nv sram. the ds17x85 also incorporates a number of enhanced functions including a silicon serial number, power-on/off control circuitry, and 2k, 4k, or 8kbytes of battery-backed nv sram. the ds17287, ds17487, and ds17887 (hereafter referred to as the ds17x87) integrate a quartz crystal and lithium energy source into a 24-pin encapsulated dip package. the ds17x85 and ds17x87 power-control circuitry allows the system to be powered on by an external stimulus such as a keyboard or by a time-and-date (wake-up) alarm. the pwr output pin is triggered by one or either of these events, and is used to turn on an external power supply. the pwr pin is under software control, so that when a task is complete, the system power can then be shut down. for all devices, the date at the end of the month is auto - matically adjusted for months with fewer than 31 days, including correction for leap years. it also operates in either 24-hour or 12-hour format with an am/pm indicator. a precision temperature-compensated circuit monitors the status of v cc . if a primary power failure is detected, the device automatically switches to a backup supply. a lithium coin cell battery can be connected to the v bat input pin on the ds17x85 to maintain time and date oper - ation when primary power is absent. the ds17x85 and ds17x87 include a v baux input used to power auxiliary functions such as pwr control. the device is accessed through a multiplexed byte-wide interface. applications embedded systems utility meters security systems network hubs, bridges, and routers features incorporates industry-standard ds12887 pc clock plus enhanced functions rtc counts seconds, minutes, hours, day, date, month, and year with leap year compensation through 2099 optional +3.0v or +5.0v operation smi recovery stack 64-bit silicon serial number power-control circuitry supports system power- on from date/time alarm or key closure crystal select bit allows operation with 6pf or 12.5pf crystal 12-hour or 24-hour clock with am and pm in 12-hour mode 114 bytes of general-purpose, battery-backed nv sram extended battery-backed nv sram ? 2048 bytes (ds17285/ds17287) ? 4096 bytes (ds17485/ds17487) ? 8192 bytes (ds17885/ds17887) ram clear function interrupt output with six independently maskable interrupt flags time-of-day alarm once per second to once per day end of clock update cycle flag programmable square-wave output automatic power-fail detect and switch circuitry available in pdip, so, or tsop package (ds17285, ds17485, ds17885) optional encapsulated dip (edip) package with integrated crystal and battery (ds17287, ds17487, ds17887) optional industrial temperature range available underwriters laboratory (ul) recognized 19-5222; rev 2; 5/16 ordering information, pin configurations, and typical operating circuit appear at end of data sheet. ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks downloaded from: http:///
voltage range on v cc pin relative to ground ... -0.3v to +6.0v operating temperature range (noncondensing) commercial......................................................... 0c to +70c industrial ......................................................... -40c to +85c storage temperature range edip ............................................................... -40c to +85c pdip, so, tsop ........................................... -55c to +125c lead temperature (soldering, 10s) ................................. +260c ( note: edip is hand or wave-soldered only.) soldering temperature (reflow) ....................................... +260c ( v cc = +4.5v to +5.5v, or v cc = +2.7v to +3.7v, t a = over the operating temperature range, unless otherwise noted. typical values are with t a = +25c, v cc = 5.0v or 3.0v and v bat = 3.0v, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units supply voltage (note 3) v cc (-5) 4.5 5.0 5.5 v (-3) 2.7 3.0 3.7 v bat input voltage v bat (note 3) 2.5 3.0 3.7 v v baux input voltage (note 3) v baux (-5) 2.5 3.0 5.2 v (-3) 3.7 input logic 1 (note 3) v ih (-5) 2.2 v cc + 0.3 v (-3) 2.0 v cc + 0.3 input logic 0 (note 3) v il (-5) -0.3 +0.8 v (-3) -0.3 +0.6 v cc power-supply current (note 4) i cc1 (-5) 25 50 ma (-3) 15 30 v cc standby current (notes 4, 5) i ccs (-5) 1.0 3.0 ma (-3) 0.5 2.0 input leakage i il -1.0 +1.0 a i/o leakage i ol (note 6) -1.0 +1.0 a output logic 1 voltage (note 3) v oh (-5), -1.0ma 2.4 v (-3), -0.4ma 2.4 output logic 0 voltage ad0Cad7, irq , sqw (note 3) v ol (-5), +2.1ma 0.4 v (-3), +0.8ma 0.4 output logic 0 voltage pwr (note 3) v ol (-5), +10ma 0.4 v (-3), +4ma 0.4 power-fail voltage (note 3) v pf (-5) 4.25 4.37 4.5 v (-3) 2.5 2.6 2.7 vrt trip point vrt trip (note 3) 1.3 v ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics downloaded from: http:///
(v cc = 0v, v bat = 3.0v, t a = over the operating range, unless otherwise noted.) (note 1) ( v cc = +4.5v to +5.5v , t a = over the operating range, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v bat or v baux current (oscillator on); t a = +25c, v bat = 3.0v i bat (note 7) 500 700 na v bat or v baux current (oscillator off) i batdr (note 7) 50 400 na parameter symbol conditions min typ max units cycle time t cyc 240 dc ns pulse width, rd or wr low pw rwl 120 ns pulse width, rd or wr high pw rwh 80 ns input rise and fall t r , t f 30 ns chip-select setup time before rd or wr t cs 20 ns chip-select hold time t ch 0 ns read-data hold time t dhr 10 50 ns write-data hold time t dhw 0 ns address setup time to ale fall t asl 20 ns address hold time to ale fall t ahl 10 ns rd or wr high setup to ale rise t asd 25 ns pulse width ale high pw ash 40 ns delay time ale low to rd low t ased 30 ns output data delay time from rd t ddr (note 8) 20 120 ns data setup time t dsw 30 ns irq release from rd t ird 2 s ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 3 dc electrical characteristicsac electrical characteristics downloaded from: http:///
( v cc = +2.7v to +3.7v , t a = over the operating range, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units cycle time t cyc 360 dc ns pulse width, rd or wr low pw rwl 200 ns pulse width, rd or wr high pw rwh 150 ns input rise and fall t r , t f 30 ns chip-select setup time before rd or wr t cs 20 ns chip-select hold time t ch 0 ns read-data hold time t dhr 10 90 ns write-data hold time t dhw 0 ns address setup time to ale fall t asl 40 ns address hold time to ale fall t ahl 10 ns rd or wr high setup to ale rise t asd 30 ns pulse width ale high pw ash 40 ns delay time ale low to rd low t ased 30 ns output data delay time from rd t ddr (note 8) 20 200 ns data setup time t dsw 70 ns irq release from rd t ird 2 s pw ash t ased pw rwh pw rwl t cs t ahl t asl t dsw t dhw t ch t asd t asd t cyc cs wr asrd ad0Cad7 write ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 4 ac electrical characteristics write timing downloaded from: http:///
ad0Cad7 cs, wr, rd high impedance don't care valid recognized recognized valid v cc t f v pf(max) v pf(min) t rec t r t asl t ddr pw ash cs wr ale rd ad0Cad7 t asd pw rwl t cs t dhr t ahl t ch t cyc pw rwh t ased irq t ird t asd ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 5 power-up/power-down timing read timing downloaded from: http:///
note 1: rtc modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. however, post-solder cleaning with water - washing techniques is acceptable, provided that ultrasonic vibrations not used to prevent damage to the crystal. note 2: limits at -40c are guaranteed by design and not production tested. note 3: all voltages are referenced to ground. note 4: all outputs are open. note 5: specified with cs = rd = wr = v cc , ale, ad0Cad7 = 0. note 6: applies to the ad0Cad7 pins, irq , and sqw when each is in a high-impedance state. note 7: measured with a 32.768khz crystal attached to x1 and x2. note 8: measured with a 50pf capacitance load plus 1ttl gate. note 9: if the oscillator is disabled in software, or if the countdown chain is in reset, t rec is bypassed, and the part becomes immediately accessible. note 10: guaranteed by design. not production tested. (t a = -40c to +85c) (note 2) (t a = +25c) (t a = +25c) (note 10) parameter symbol conditions min typ max units recovery at power-up t rec (note 9) 20 150 ms v cc fall time, v pf(max) to v pf(min) t f 300 s v cc fall time, v pf(max) to v pf(min) t r 0 s parameter symbol conditions min typ max units expected data retention t dr (note 9) 10 years parameter symbol conditions min typ max units capacitance on all input pins except x1 c in (note 10) 12 pf capacitance on irq , sqw, and dq0Cdq7 pins c io (note 10) 12 pf parameter conditions input pulse levels: 0 to 3.0v output load including scope and jig: 50pf + 1ttl gate input and output timing measurement reference levels: input/output: v il max and v ih min input pulse rise and fall times: 5ns ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 6 power-up/power-down characteristicsdata retention (ds17x87 only) capacitance ac test conditions warning: negative undershoots below -0.3v while the part is in battery-backed mode can cause loss of data. downloaded from: http:///
(v cc = +3.3v, t a = +25c, unless otherwise noted.) pin name function 24 28 1 8 pwr active-low power-on reset. this open-drain output pin is intended for use as an on/off control for the system power. with v cc voltage removed from the device, pwr can be automatically activated from a kickstart input by the ks pin or from a wake-up interrupt. once the system is powered on, the state of pwr can be controlled by bits in the control registers. the pwr pin can be connected through a pullup resistor to a positive supply. for 5v operation, the voltage of the pullup supply should be no greater than 5.7v. for 3v operation, the voltage on the pullup supply should be no greater than 3.9v. 2, 3 9, 10 x1, x2 connections for standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a speciied load capacitance (c l ) of 6pf or 12.5pf. pin x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator, pin x2, is left unconnected if an external oscillator is connected to pin x1. these pins are missing (n.c.) on the edip package. 4C11 12C17, 19, 20 ad0Cad7 multiplexed bidirectional address/data bus. the addresses are presented during the irst portion of the bus cycle and latched into the device by the falling edge of ale. write data is latched by the rising edge of wr . in a read cycle, the device outputs data during the latter portion of the rd low. the read cycle is terminated and the bus returns to a high-impedance state as rd transitions high. 12, 16 21, 22, 26 gnd ground supply current vs. temperature ds17285/87 toc02 temperature (c) supply current (na) 65 50 35 20 5 -10 -25 300 350 400250 -40 80 v bat = 3.0v oscillator frequency vs. supply voltage ds17285/87 toc03 supply voltage (v) oscillator frequency (hz) 5.0 4.5 4.0 3.5 3.0 32768.1 32768.2 32768.3 32768.4 32768.5 32768.6 32768.732768.0 2.5 5.5 supply current vs. input voltage ds17285/87 toc01 v bat (v) supply current (na) 3.5 3.3 3.0 2.8 250 300 350 400200 2.5 3.8 v cc = 0v ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 7 typical operating characteristics pin description downloaded from: http:///
pin name function 24 28 13 23 cs active-low chip-select input. this pin must be asserted low during a bus cycle for the device to be accessed. cs must be kept in the active state during rd and wr . bus cycles that take place without asserting cs latch addresses, but no access occurs. 14 24 ale address latch enable input, active high. this input pin is used to demultiplex the address/data bus. the falling edge of ale causes the address to be latched within the device. 15 25 wr active-low write input. this pin deines the period during which data is written to the addressed register. 17 27 rd active-low read input. this pin identiies the period when the device drives the bus with read data. it is an enable signal for the output buffers of the device. 18 28 ks active-low kickstart input. when v cc is removed from the device, the system can be powered on in response to an active-low transition on the ks pin, as might be generated from a key closure. v baux must be present and auxiliary-battery-enable bit (abe) must be set to 1 if the kickstart function is used, and the ks pin must be pulled up to the v baux supply. while v cc is applied, the ks pin can be used as an interrupt input. if not used, ks must be grounded and abe set to 0. 19 1 irq active-low interrupt request. this pin is an active-low output that can be used as an interrupt input to a processor. the irq output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. to clear the irq pin, the application software must clear all enabled lag bits contributing to the pins active state. when no interrupt conditions are present, the irq level is in the high-impedance state. multiple interrupting devices can be connected to an irq bus, provided that they are all open drain. the irq pin requires an external pullup resistor to v cc . 20 2 v bat connection for primary battery. this supply input is used to power the normal clock functions when v cc is absent. diodes placed in series between v bat and the battery can prevent proper operation. if v bat is not required, the pin must be grounded. ul recognized to ensure against reverse charging current when used with a lithium battery ( www.maximintegrated.com/qa/ info/ul ). this pin is missing (n.c.) on the edip package. ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 8 pin description (continued) downloaded from: http:///
pin name function 24 28 21 3 rclr active-low ram clear input. this pin is used to clear (set to logic 1) all the 114 bytes of general-purpose ram but does not affect the ram associated with the real time clock or extended ram. rclr may be invoked while the part is powered from any supply. the rclr function is designed to be used via a human interface (shorting to ground manually or by a switch) and not to be driven with external buffers. this pin is internally pulled up. do not use an external pullup resistor on this pin. 22 4 v baux auxiliary battery input. required for kickstart and wake-up functions. this input also supports clock/calendar and user ram if v bat is at lower voltage or is not used. a standard +3v lithium cell or other energy source can be used. diodes placed in series between v baux and the battery may prevent proper operation. ul recognized to ensure against reverse charging current when used with a lithium battery ( www.maximintegrated.com/qa/info/ul/ ). for 3v v cc operation, v baux must be held between +2.5v and +3.7v. for 5v v cc operation, v baux must be held between +2.5v and +5.2v. if v baux is not used it should be grounded and the auxiliary-battery-enable bit bank 1, register 4bh, should = 0. 23 5 sqw square-wave output. when v cc rises above v pf , bits dv1 and e32k are set to 1. this condition enables a 32khz square-wave output. a square wave is output if either sqwe = 1 or e32k = 1. if e32k = 1, then 32khz is output regardless of the other control bits. if e32k = 0, then the output frequency is dependent on the control bits in register a. the sqw pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the rtc. the frequency of the sqw pin can be changed by programming register a, as shown in table 3. the sqw signal can be turned on and off using the sqwe bit in register b or the e32k bit in extended register 4bh. a 32khz square wave is also available when v cc is less than v pf if e32k = 1, abe = 1, and voltage is applied to the v baux pin. when disabled, sqw is high impedance when v cc is below v pf . 24 6, 7 v cc dc power pin for primary power supply. when v cc is applied within normal limits, the device is fully accessible and data can be written and read. when v cc is below v pf reads and writes are inhibited. 2, 3, 16, 20 (ds17x87 only) 11, 18 n.c. no connection ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 9 pin description (continued) downloaded from: http:///
figure 1. functional diagram x1 oscillator power control x2 ds17x87 only v bat gnd divide by 8 registers a, b, c, d clock/calendar update logic extended user ram 2k/4k/8k bytes select extended ram addr/ data registers extended control/ status registers 64-bit serial number century counter date alarm rtc address-2 rtc address-3 divide by 64 divide by 64 16:1 mux square- wave generator sqw irqpwr ks rlcr irq generator v cc v baux bus interface cs wr rd ale ad0Cad7 clock/calendar and alarm registers buffered clock/ calendar and alarm registers user ram 114 bytes ram clear logic ds17x85/87 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 10 downloaded from: http:///
detailed description the ds17x85 is a successor to the ds1285 real-time clock (rtc). the device provides 18 bytes of real-time clock/calendar, alarm, and control/status registers and 114 bytes of nonvolatile battery-backed ram. the device also provides additional extended ram in either 2k/4k/8kbytes (ds17285/ds17485/ds17885). a time-of-day alarm, six maskable interrupts with a common interrupt output, and a programmable square-wave output are available. it also operates in either 24-hour or 12-hour format with an am/ pm indicator. a precision temperature-compensated cir - cuit monitors the status of v cc . if a primary power-supply failure is detected, the device automatically switches to a backup supply. the backup supply input supports a primary battery, such as a lithium coin cell. the device is accessed by a multiplexed address/data bus. oscillator circuit the ds17x85 uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crystal parameters for the external crystal, and figure 2 shows a functional schematic of the oscillator circuit. the oscil - lator is controlled by an enable bit in the control register. oscillator startup times are highly dependent upon crystal characteristics, pc board leakage, and layout. high esr and excessive capacitive loads are the major contributors to long startup times. a circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. an external 32.768khz oscillator can also drive the ds17x85. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left unconnected. clock accuracy the accuracy of the clock is dependent upon the accu - racy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capaci - tive load for which the crystal was trimmed. additional error will be added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit may result in the clock running fast. figure 3 shows a typical pc board layout for isolation of the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. clock accuracy (ds17287, ds17487, and ds17887) the encapsulated dip (edip) modules are trimmed at the factory to 1 minute per month accuracy at 25c. figure 2. oscillator circuit showing internal bias networkfigure 3. layout example table 1. crystal specifications* (ds17x85 only) * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi - tional specifications. parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 50 k? load capacitance c l 6 or 12.5 pf countdown chain x1 x2 crystal c l 1 c l 2 rtc registers ds17285/87ds17485/87 ds17885/87 local ground plane (top layer) crystal gnd x2 x1 note: avoid routing signal lines in the crosshatched area (upper left quadrant) of the package unless there is a ground plane between the signal line and the device package. ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 11 downloaded from: http:///
power-down/power-up considerations the rtc function continues to operate, and all the ram, time, calendar, and alarm memory locations remain non - volatile regardless of the level of the v cc input. v bat or v baux must remain within the minimum and maximum limits when v cc is not applied. when v cc falls below v pf , the device inhibits all access, putting the part into a low-power mode. when v cc is applied and exceeds v pf (power-fail trip point), the device becomes acces - sible after t rec , if the oscillator is running and the oscil - lator countdown chain is not in reset (register a). this time period allows the system to stabilize after power is applied. if the oscillator is not enabled, the oscilla - tor enable bit is enabled on powerup, and the device becomes immediately accessible. power control the power control function is provided by a precise, temperature-compensated voltage reference and a com - parator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the device inhibits read and write access. if v pf is less than v bat , the device power is switched from v cc to the higher of v bat or v baux when v cc drops below v pf . if v pf is greater than the higher of v bat or v baux , the device power is switched from v cc to the higher of v bat or v baux when v cc drops below the higher backup source. the registers are maintained from the v bat or v baux source until v cc is returned to nominal levels. after v cc returns above v pf , read and write access is allowed after t rec . time, calendar, and alarm locations the time and calendar information is obtained by read - ing the appropriate register bytes. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. the contents of the 12 time, calendar, and alarm bytes can be either binary or binary-coded deci - mal (bcd) format. tables 3a and 3b show the bcd and binary formats of the 12 time, date, and alarm registers, control registers a to d, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching is explained later in this text). the day-of-week register increments at midnight, incre - menting from 1 through 7. the day-of-week register is used by the daylight saving function, and so the value 1 is defined as sunday. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. before writing the internal time, calendar, and alarm registers, the set bit in register b should be written to logic 1 to prevent updates from occurring while access is being attempted. in addition to writing the 12 time, calen - dar, and alarm registers in a selected format (binary or bcd), the data mode bit (dm) of register b must be set to the appropriate logic level. all 12 time, calendar, and alarm bytes must use the same data mode. the set bit in register b should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. once initialized, the real time clock makes all updates in the selected mode. the data mode cannot be changed without reinitializing the 12 data bytes. tables 3a and 3b show the bcd and binary formats of the 12 time, calendar, and alarm locations. the 24-12 bit cannot be changed without reinitializing the hour locations. when the 12-hour format is selected, the high order bit of the hours byte represents pm when it is logic 1. the time, calendar, and alarm bytes are always accessible because they are double-buffered. once per second, the eight bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., may not correlate. the probability of reading incor - rect time and calendar data is low. several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. table 2. power control supply condition read/write access powered by v cc < v pf , v cc < (v bat | v baux ) no v bat or v baux v cc < v pf , v cc > (v bat | v baux ) no v cc v cc > v pf , v cc < (v bat | v baux ) yes v cc v cc > v pf , v cc > (v bat | v baux ) yes v cc ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 12 downloaded from: http:///
the alarm bytes can be used in two ways. first, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day, if the alarm enable bit is high. in this mode, the 0 bits in the alarm registers and the cor - responding time registers must always be written to 0 (see table 3a and 3b). writing the 0 bits in the alarm and/or time registers to 1 can result in undefined operation. the second use condition is to insert a dont care state in one or more of the alarm bytes. the dont care code is any hexadecimal value from c0 to ff. the two most sig - nificant bits of each byte set the dont care condition when at logic 1. an alarm will be generated each hour when the dont care bits are set in the hours byte. similarly, an alarm is generated every minute with dont care codes in the hours and minute alarm bytes. an alarm is generated every second with dont care codes in the hours, minutes, and seconds alarm bytes. all 128 bytes can be directly written or read except for the following: 1) registers c and d are read-only. 2) bit 7 of register a is read-only. 3) the msb of the seconds byte is read-only. note: unless otherwise specified, the state of the registers is not defined when power is first applied. except for the seconds reg - ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits. table 3a. time, calendar, and alarm data modesbcd mode (dm = 0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00C59 01h 0 10 seconds seconds seconds alarm 00C59 02h 0 10 minutes minutes minutes 00C59 03h 0 10 minutes minutes minutes alarm 00C59 04h am /pm 0 0 10 hour hours hours 1C12 + am /pm 00C23 0 10 hour 05h am /pm 0 0 10 hour hours hours alarm 1C12 + am /pm 00C23 0 10 hour 06h 0 0 0 0 0 day day 01C07 07h 0 0 10 date date date 01C31 08h 0 0 0 10 month month month 01C12 09h 10 year year year 00C99 0ah uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 control 0bh set pie aie uie sqwe dm 24/12 dse control 0ch irqf pf af uf 0 0 0 0 control 0dh vrt 0 0 0 0 0 0 0 control bank 1, 48h 10 century century century 00C99 bank 1, 49h 10 date date date alarm 01C31 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 13 downloaded from: http:///
control registers the four control registers (a, b, c, and d) reside in both bank 0 and bank 1. these registers are accessible at all times, even during the update cycle. bit 7: update in progress (uip). this bit is a status flag that can be monitored. when the uip bit is 1, the update transfer will soon occur. when uip is 0, the update trans - fer does not occur for at least 244s. the time, calendar, and alarm information in ram is fully available for access when the uip bit is 0. the uip bit is read-only. writing the set bit in register b to 1 inhibits any update transfer and clears the uip status bit. bits 6, 5, and 4: dv2, dv1, and dv0. these bits are used to turn the oscillator on or off and to reset the count- down chain. a pattern of 01x is the only combination of bits that turns the oscillator on and allows the rtc to keep time. a pattern of 11x enables the oscillator but holds the countdown chain in reset. the next update occurs at 500ms after a pattern of 01x is written to dv0, dv1, and dv2. dv0 is used to select bank 0 or bank 1 as defined in table 5. when dv0 is set to 0, bank 0 is selected. when dv0 is set to 1, bank 1 is selected. note: unless otherwise specified, the state of the registers is not defined when power is first applied. except for the seconds reg - ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits. table 3b. time, calendar, and alarm data modesbinary mode (dm = 1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 0 seconds seconds 00C3b 01h 0 0 seconds seconds alarm 00C3b 02h 0 0 minutes minutes 00C3b 03h 0 0 minutes minutes alarm 00C3b 04h am /pm 0 0 0 hours hours 1C0c + am/pm 00C17 0 hours 05h am /pm 0 0 0 hours hours alarm 1C0c + am/pm 00C17 0 hours 06h 0 0 0 0 0 day day 01C07 07h 0 0 0 date date 01C1f 08h 0 0 0 0 month month 01C0c 09h 0 year year 00C63 0ah uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 control 0bh set pie aie uie sqwe dm 24/12 dse control 0ch irqf pf af uf 0 0 0 0 control 0dh vrt 0 0 0 0 0 0 0 control bank 1, 48h 10 century century century 00C63 bank 1, 49h 10 date date date alarm 01C1f msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 14 register a (0ah) downloaded from: http:///
bits 3 to 0: rate selector bits (rs3 to rs0). these four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. the tap selected can be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user can do one of the following: 1) enable the interrupt with the pie bit; 2) enable the sqw output pin with the sqwe or e32k bits; 3) enable both at the same time and the same rate; or 4) enable neither. table 4 lists the periodic interrupt rates and the square - wave frequencies that can be chosen with the rs bits. * rs3 to rs0 determine periodic interrupt rates as listed for e32k = 0. table 4. periodic interrupt rate and square-wave output frequency ext reg b select bits register a t pi periodic interrupt rate sqw output frequency e32k rs3 rs2 rs1 rs0 0 0 0 0 0 none none 0 0 0 0 1 3.90625ms 256hz 0 0 0 1 0 7.8125ms 128hz 0 0 0 1 1 122.070fs 8.192khz 0 0 1 0 0 244.141fs 4.096khz 0 0 1 0 1 488.281fs 2.048khz 0 0 1 1 0 976.5625fs 1.024khz 0 0 1 1 1 1.953125ms 512hz 0 1 0 0 0 3.90625ms 256hz 0 1 0 0 1 7.8125ms 128hz 0 1 0 1 0 15.625ms 64hz 0 1 0 1 1 31.25ms 32hz 0 1 1 0 0 62.5ms 16hz 0 1 1 0 1 125ms 8hz 0 1 1 1 0 250ms 4hz 0 1 1 1 1 500ms 2hz 1 x x x x * 32.768khz ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 15 downloaded from: http:///
bit 7: set. when the set bit is 0, the update transfer functions normally by advancing the counts once per sec - ond. when the set bit is written to 1, any update transfer is inhibited, and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. read cycles can be executed in a similar manner. set is a read/write bit and is not affected by any internal functions of the ds17x85. bit 6: periodic interrupt enable (pie). this bit is a read/ write bit that allows the periodic interrupt flag (pf) bit in register c to drive the irq pin low. when pie is set to 1, periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3Crs0 bits of register a. a 0 in the pie bit blocks the irq output from being driven by a periodic interrupt, but the pf bit is still set at the periodic rate. pie is not modified by any internal ds17x85 functions. bit 5: alarm interrupt enable (aie). this bit is a read/ write bit that, when set to 1, permits the alarm flag (af) bit in register c to assert irq . an alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes, including a dont care alarm code of binary 11xxxxxx. when the aie bit is set to 0, the af bit does not initiate the irq signal. the internal functions of the ds17x285/87 do not affect the aie bit. bit 4: update-ended interrupt enable (uie). this bit is a read/write bit that enables the update-end flag (uf) bit in register c to assert irq . the set bit going high clears the uie bit. bit 3: square-wave enable (sqwe). when this bit is set to 1 and e32k = 0, a square-wave signal at the frequency set by rs3Crs0 is driven out on the sqw pin. when the sqwe bit is set to 0 and e32k = 0, the sqw pin is held low. sqwe is a read/write bit. sqwe is set to 1 when v cc is powered up. bit 2: data mode (dm). this bit indicates whether time and calendar information is in binary or bcd format. the program sets the dm bit to the appropriate format and can be read as required. this bit is not modified by internal functions. a 1 in dm signifies binary data, while a 0 in dm specifies binary-coded decimal (bcd) data. bit 1: 24/12 control (24/12). this bit establishes the for - mat of the hours byte. a 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. this bit is read/write and is not affected by internal functions. bit 0: daylight saving enable (dse). this bit is a read/ write bit that enables two daylight saving adjustments when dse is set to 1. on the first sunday in april, the time increments from 1:59:59am to 3:00:00am. on the last sunday in october when the time first reaches 1:59:59am, it changes to 1:00:00am. when dse is enabled, the internal logic tests for the first/last sunday condition at midnight. if the dse bit is not set when the test occurs, the daylight saving function does not operate correctly. these adjustments do not occur when the dse bit is zero. this bit is not affected by internal functions. msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 16 register b (0bh) downloaded from: http:///
bit 7: interrupt request flag (irqf). this bit is set to 1 when any of the following are true: pf = pie = 1 wf = wie = 1 af = aie = 1 kf = kse = 1 uf = uie = 1 rf = rie = 1 any time the irqf bit is 1, the irq pin is driven low. flag bits pf, af, and uf are cleared after reading register c. bit 6: periodic interrupt flag (pf). this is a read-only bit that is set to 1 when an edge is detected on the selected tap of the divider chain. the rs3Crs0 bits establish the periodic rate. pf is set to 1 independent of the state of the pie bit. when both pf and pie are 1s, the irq signal is active and sets the irqf bit. reading register c clears this bit. bit 5: alarm interrupt flag (af). a 1 in this bit indicates that the current time has matched the alarm time. if the aie bit is also 1, the irq pin goes low and a 1 appears in the irqf bit. reading register c clears this bit. bit 4: update-ended interrupt flag (uf). this bit is set after each update cycle. when the uie bit is set to 1, the 1 in uf causes the irqf bit to be 1, which asserts irq . reading register c clears this bit. bits 3 to 0: unused. these unused bits always read 0 and cannot be written. register d (0dh) bit 7: valid ram and time (vrt). this bit indicates the condition of the battery connected to the v bat and v baux pin. if either supply is above the internal voltage threshold, vrt trip , the bit will be high. this bit is not writeable and should always be a 1 when read. if a 0 is ever present, an exhausted internal lithium energy source is indicated and both the contents of the rtc data and ram data are questionable. bits 6 to 0: unused. these bits cannot be written and, when read, always read 0. msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqf pf af uf 0 0 0 0 msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt 0 0 0 0 0 0 0 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 17 register c (0ch)register d (0dh) downloaded from: http:///
nonvolatile ram the user ram bytes are not dedicated to any special function within the ds17x85. they can be used by the processor program as battery-backed memory and are fully available during the update cycle. the user ram is divided into two separate memory banks. when the bank 0 is selected, the 14 real-time clock registers and 114 bytes of user ram are acces - sible. when bank 1 is selected, an additional 2kbytes, 4kbytes, or 8kbytes of user ram are accessible through the extended ram address and data registers. interrupts the rtc includes six separate, fully automatic sources of interrupt for a processor: 1) alarm interrupt 2) periodic interrupt 3) update-ended interrupt 4) wake-up interrupt 5) kickstart interrupt 6) ram clear interrupt the conditions that generate each of these independent interrupt conditions are described in detail in other sec - tions of this data sheet. this section describes the overall control of the interrupts. the application software can select which interrupts, if any, are to be used. there are 6 bits, including 3 bits in register b and 3 bits in extended register 4b, that enable the interrupts. the extended register locations are described later. writing logic 1 to an interruptenable bit permits that interrupt to be initiated when the event occurs. a logic 0 in the interrupt-enable bit prohibits the irq pin from being asserted from that interrupt condi - tion. if an interrupt flag is already set when an interrupt is enabled, irq is immediately set at an active level, although the event initiating the interrupt condition might have occurred much earlier. therefore, there are cases where the software should clear these earlier generated interrupts before first enabling new interrupts. when an interrupt event occurs, the relating flag bit is set to logic 1 in register c or in extended register 4a. these flag bits are set regardless of the setting of the corresponding enable bit located either in register b or in extended register 4b. the flag bits can be used in a poll - ing mode without enabling the corresponding enable bits. however, care should be taken when using the flag bits of register c as they are automatically cleared to 0 immedi - ately after they are read. double latching is implemented on these bits so that set bits remain stable throughout the read cycle. all bits that were set are cleared when read and new interrupts that are pending during the read cycle are held until after the cycle is completed. one, two, or three bits can be set when reading register c. each used flag bit should be examined when read to ensure that no interrupts are lost. the flag bits in extended register 4a are not automati - cally cleared following a read. instead, each flag bit can be cleared to 0 only by writing 0 to that bit. when using the flag bits with fully enabled interrupts, the irq line is driven low when an interrupt flag bit is set and its corresponding enable bit is also set. irq is held low as long as at least one of the six possible interrupt sources has its flag and enable bits both set. the irqf bit in register c is 1 whenever the irq pin is being driven low as a result of one of the six possible active sources. therefore, determination that the ds17x85/ds17x87 initi - ated an interrupt is accomplished by reading register c and finding irqf = 1. irqf remains set until all enabled interrupt flag bits are cleared to 0. oscillator control bits a pattern of 01x in bits 4 to 6 of register a turns the oscil - lator on and enables the countdown chain. a pattern of 11x (dv2 = 1, dv1 = 1, dv0 = x) turns the oscillator on, but holds the countdown chain of the oscillator in reset. all other combinations of bits 4 to 6 keep the oscillator off. when the ds17x87 is shipped from the factory, the internal oscillator is turned off. this feature prevents the lithium energy cell from being used until it is installed in a system. square-wave output selection thirteen of the 15 divider taps are made available to a 1-of-16 multiplexer, as shown in figure 1. the square wave and periodic interrupt generators share the output of the multiplexer. the rs0Crs3 bits in register a establish the output frequency of the multiplexer. these frequen - cies are listed in table 4. once the frequency is selected, the output of the sqw pin can be turned on and off under program control with the square-wave enable bit (sqwe). if e32k = 0, the square-wave output is determined by the rs3 to rs0 bits. if e32k = 1, a 32khz square wave is output on the sqw pin, regardless of the rs3 to rs0 bits state. if e32k = abe = 1 and a valid voltage is applied to v baux , a 32khz square wave is output on sqw when v cc is below v tp . ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 18 downloaded from: http:///
periodic interrupt selection the periodic interrupt causes the irq pin to go to an active state from once every 500ms to once every 122s. this function is separate from the alarm interrupt, which can be output from once per second to once per day. the periodic interrupt rate is selected using the same register a bits that select the squarewave frequency (see table 4). changing the register a bits affects both the square-wave frequency and the periodic interrupt output. however, each function has a separate enable bit in register b. the sqwe and e32k bits control the square-wave output. similarly, the periodic interrupt is enabled by the pie bit in register b. the periodic interrupt can be used with soft - ware counters to measure inputs, create output intervals, or await the next needed software function. update cycle the ds17x85 executes an update cycle once per second regardless of the set bit in register b. when the set bit in register b is set to 1, the user copy of the double- buffered time, calendar, and alarm bytes is frozen and does not update as the time increments. however, the time countdown chain continues to update the internal copy of the buffer. this feature allows time to maintain accuracy independent of reading or writing the time, cal - endar, and alarm buffers, and also guarantees that time and calendar information is consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a dont care code is present in all alarm locations. there are three methods that can handle access of the rtc that avoid any possibility of accessing inconsistent time and calendar data. the first method uses the update- ended interrupt. if enabled, an interrupt occurs after every update cycle that indicates that over 999ms are available to read valid time and date information. if this interrupt is used, the irqf bit in register c should be cleared before leaving the interrupt routine. a second method uses the update-in-progress (uip) bit in register a to determine if the update cycle is in progress. the uip bit pulses once per second. after the uip bit goes high, the update transfer occurs 244s later. if a low is read on the uip bit, the user has at least 244s before the time/calendar data is changed. therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244s. the third method uses a periodic interrupt to determine if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c (see figure 4). periodic interrupts that occur at a rate of greater than t buc allow valid time and date information to be reached at each occurrence of the periodic interrupt. the reads should be complete within 1 (t pi/2 + t buc ) to ensure that data is not read during the update cycle. figure 4. uip and periodic interrupt timing uip uf pf t buc = delay time before update cycle = 244s. 1 second t pi t pi/2 t pi/2 t buc ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 19 downloaded from: http:///
extended functions the extended functions provided by the ds17x85/ ds17x87 that are new to the ramified rtc family are accessed by a software-controlled bank-switching scheme, as illustrated in table 5. in bank 0, the clock/ calendar registers and 50 bytes of user ram are in the same locations as for the ds1287. as a result, existing routines implemented within bios, dos, or application software packages can gain access to the ds17x85/ ds17x87 clock registers with no changes. also in bank 0, an extra 64 bytes of ram are provided at addresses just above the original locations for a total of 114 directly addressable bytes of user ram. when bank 1 is selected, the clock/calendar registers and the original 50 bytes of user ram still appear as bank 0. however, the extended registers that provide control and status for the extended functions are accessed in place of the additional 64 bytes of user ram. the major extended functions controlled by the extended registers are listed below: ? 64-bit silicon serial number ? century counter ? rtc write counter ? date alarm ? auxiliary battery control/status ? wake-up ? kickstart? ram clear control/status ? extended ram access the bank selection is controlled by the state of the dv0 bit in register a. to access bank 0 the dv0 bit should be written to a 0. to access bank 1, dv0 should be written to 1. register locations designated as reserved in the bank 1 map are reserved for future use by dallas semiconductor. bits in these locations cannot be written and return a 0 if read. silicon serial number a unique 64-bit lasered serial number is located in bank 1, registers 40hC47h. this serial number is divided into three parts. the first byte in register 40h contains a model num - ber to identify the device type of the ds17x85/ds17x87. registers 41hC46h contain a unique binary number. register 47h contains a crc byte used to validate the data in registers 40hC46h. the crc polynomial is x 8 + x 5 + x 4 + 1. see figure 5. all 8 bytes of the serial number are read-only registers. the ds17x85/ds17x87 is manu - factured such that no two devices contain an identical number in locations 41hC47h. figure 5. crc polynomial device model number ds17285/87 72h ds17485/87 74h ds17885/87 78h 1st stage 2nd stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage input data polynomial = x 8 + x 5 + x 4 + 1 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 20 downloaded from: http:///
note: reserved bits can be written to any value, but always read back as zeros. table 5. extended bank register bank definition bank 0 bank 1 dv0 = 0 dv0 = 1 00h 0dh timekeeping and control 00h 0dh timekeeping and control 0eh 3fh 50 bytes C user ram 0eh 3fh 50 bytes C user ram 40h 40h model number byte 41h 1st byte serial number 42h 2nd byte serial number 43h 3rd byte serial number 44h 4th byte serial number 45h 5th byte serial number 46h 6th byte serial number 47h crc byte 48h century byte 49h date alarm 4ah extended control register 4a 4bh extended control register 4b 4ch reserved 4dh reserved 4eh rtc address C 2 4fh rtc address C 3 64 bytes C user ram 50h extended ram address lsb 51h extended ram address msb 52h reserved 53h extended ram data port 54h reserved 55h reserved 56h reserved 57h reserved 58h reserved 59h reserved 5ah reserved 5bh reserved 5ch reserved 5dh reserved 5eh rtc write counter 7fh 5fh7fh reserved ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 21 downloaded from: http:///
century counter a register has been added in bank 1, location 48h, to keep track of centuries. the value is read in either binary or bcd according to the setting of the dm bit. rtc write counter an 8-bit counter located in extended register bank 1, 5eh, counts the number of times the rtc is written to. this counter is incremented on the rising edge of the wr sig - nal every time that the cs signal qualifies it. this counter is a read-only register and rolls over after 256 rtc write pulses. this counter can be used to determine if and how many rtc writes have occurred since the last time this register was read. auxiliary battery the v baux input is provided to supply power from an auxiliary battery for the ds17x85/ds17x87 kickstart, wake-up, and sqw output in the absence of v cc func - tions. this power source must be available to use these auxiliary functions when no v cc is applied to the device. the auxiliary battery enable (abe; bank 1, register 04bh) bit in extended control register 4b is used to turn the auxiliary battery on and off for the above functions in the absence of v cc . when set to 1, v baux battery power is enabled; when cleared to 0, v baux battery power is disabled to these functions. in the ds17x85/ds17x87, this auxiliary battery can be used as the primary backup power source for maintain - ing the clock/calendar, user ram, and extended external ram functions. this occurs if the v bat pin is at a lower voltage than v baux . if the ds17x85 is to be backed up using a single battery with any auxiliary functions enabled, then v baux should be used and v bat should be grounded. if v baux is not to be used, it should be grounded and abe should be cleared to 0. wake-up/kickstart the ds17x85/ds17x87 incorporates a wake-up feature that powers on the system at a predetermined date and time through activation of the pwr output pin. in addition, the kickstart feature allows the system to be powered up in response to a low-going transition on the ks pin, with - out operating voltage applied to the v cc pin. as a result, system power can be applied upon such events as a key closure or modem ring-detect signal. to use either the wake-up or the kickstart functions, the ds17x85/ds17x87 must have an auxiliary battery con - nected to the v baux pin, the oscillator must be running, and the countdown chain must not be in reset (register a dv2, dv1, dv0 = 01x). if dv2 and dv1 are not in this required state, the pwr pin is not driven low in response to a kick - start or wake-up condition while in battery-backed mode.the wake-up feature is controlled through the wake-up interrupt-enable bit in extended control register 4b (wie, bank 1, 04bh). setting wie to 1 enables the wake-up feature, clearing wie to 0 disables it. similarly, the kick - start interrupt-enable bit in extended control register 4b (kse, bank 1, 04bh) controls the kickstart feature. a wake-up sequence occurs as follows: when wake-up is enabled through wie = 1 while the system is powered down (no v cc voltage), the clock/calendar monitors the current date for a match condition with the date alarm reg - ister (bank 1, register 049h). with the date alarm register, the hours, minutes, and seconds alarm bytes in the clock/ calendar register map (bank 0, registers 05h, 03h, and 01h) are also monitored. as a result, a wake-up occurs at the date and time specified by the date, hours, minutes, and seconds alarm register values. this additional alarm occurs regardless of the programming of the aie bit (bank 0, register b, 0bh). when the match condition occurs, the pwr pin is automatically driven low. this output can be used to turn on the main system power supply that provides v cc voltage to the ds17x85/ds17x87 as well as the other major components in the system. also at this time, the wake-up flag (wf, bank 1, register 04ah) is set, indicating that a wake-up condition has occurred. a kickstart sequence occurs when kickstarting is enabled through kse = 1. while the system is powered down, the ks input pin is monitored for a low-going transition of minimum pulse width t kspw . when such a transition is detected, the pwr line is pulled low, as it is for a wake-up condition. also at this time, the kickstart flag (kf, bank 1, register 04ah) is set, indicating that a kickstart condition has occurred. ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 22 downloaded from: http:///
(t a = +25c) the timing associated with both the wake-up and kick - starting sequences is illustrated in the wake-up/kickstart timing diagram (figure 6). the timing associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram. the occurrence of either a kickstart or wake-up condition causes the pwr pin to be driven low, as described above. during interval 1, if the supply voltage on the ds17x85/ ds17x87 v cc pin rises above the greater of v bat or v pf before the power-on timeout period (t poto ) expires, then pwr remains at the active-low level. if v cc does not rise above the greater of v bat or v pf in this time, then the pwr output pin is turned off and returns to its high- impedance level. in this event, the irq pin also remains tri-stated. the interrupt flag bit (either wf or kf) associ - ated with the attempted power-on sequence remains set until cleared by software during a subsequent system power-on. if v cc is applied within the timeout period, then the sys - tem power-on sequence continue as shown in intervals 2 to 5 in the timing diagram. during interval 2, pwr remains active and irq is driven to its active-low level, indicating that either wf or kf was set in initiating the power-on. in the diagram ks is assumed to be pulled up to the v baux supply. also at this time, the pab bit is automati - cally cleared to 0 in response to a successful power-on. the pwr line remains active as long as the pab remains cleared to 0. figure 6. wake-up/kickstart timing diagram note: wake-up/kickstart timeout is generated only when the oscillator is enabled and the countdown chain is not reset. table 6. wake-up/kickstart timing parameter symbol conditions min typ max units kickstart-input pulse width t kspw 2 s wake-up/kickstart power-on timeout t poto 2 s v bat v bat v ih t kspw t potp v ih v ih 1 2 3 4 5 v il v il high-impedancehigh-impedance v il v pf v pf 0v0v *conditionvpf < vbat *this condition can occur with the 3v device.note: the time intervals shown above are referenced in the wake-up/kickstart section. *conditionvbat > vpf wf/kf(internal) kspwr irq ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 23 downloaded from: http:///
at the beginning of interval 3, the system processor has begun code execution and clears the interrupt condition of wf and/or kf by writing zeros to both of these control bits. as long as no other interrupt within the ds17x85/ ds17x87 is pending, the irq line is taken inactive once these bits are reset. execution of the application software can proceed. during this time, the wake-up and kickstart functions can be used to generate status and interrupts. wf is set in response to a date, hours, minutes, and seconds match condition. kf is set in response to a low- going transition on ks . if the associated interrupt-enable bit is set (wie and/or kse), the irq line is driven active low in response to enabled event. in addition, the other possible interrupt sources within the ds17885/ds17887 can cause irq to be driven low. while system power is applied, the on-chip logic always attempts to drive the pwr pin active in response to the enabled kickstart or wake-up condition. this is true even if pwr was previ - ously inactive as the result of power being applied by some means other than wake-up or kickstart. the system can be powered down under software control by setting the pab bit to logic 1. this causes the open- drain pwr pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in the timing diagram. as v cc voltage decays, the irq output pin is placed in a high-impedance state when v cc goes below v pf . if the system is to be again powered on in response to a wake-up or kickstart, then the wf and kf flags should be cleared, and wie and/or kse should be enabled prior to setting the pab bit. during interval 5, the system is fully powered down. battery backup of the clock calendar and nv ram is in effect and irq is tri-stated, and monitoring of wake-up and kickstart takes place. if prs = 1, pwr stays active; otherwise, if prs = 0, pwr is high impedance. ram clear the ds17x85/ds17x87 provide a ram clear function for the 114 bytes of user ram. when enabled, this function can be performed regardless of the condition of the v cc pin. the ram clear function is enabled or disabled through the ram clear-enable bit (rce; bank 1, register 04bh). when this bit is set to logic 1, the 114 bytes of user ram is cleared (all bits set to 1) when an active-low transition is sensed on the rclr pin. this action has no effect on either the clock/calendar settings or the contents of the extended ram. the ram clear flag (rf, bank 1, register 04ah) is set when the ram clear operation has been completed. if v cc is present at the time of the ram clear and rie = 1, the irq line is also driven low upon comple - tion. writing a zero to the rf bit clears the interrupt con - dition. the irq line then returns to its inactive high level, provided there are no other pending interrupts. once the rclr pin is activated, all read/write accesses are locked out for a minimum recover time, specified as t rec in electrical characteristics . when rce is cleared to 0, the ram clear function is disabled. the state of the rclr pin has no effect on the contents of the user ram, and transitions on the rclr pin have no effect on rf. extended ram the ds17x85/ds17x87 provide 2k, 4k, or 8k x 8 of onchip sram that is controlled as nonvolatile storage sustained from a lithium battery. on power-up, the ram is taken out of write-protect status by the internal power-ok sig - nal (pok) generated from the write-protect circuitry. the on-chip sram is accessed through the eight multiplexed address/data lines ad7 to ad0. three on-chip latch regis - ters control access to the sram. two registers are used to hold the sram address, and the other register is used to hold read/write data. access to the extended ram is controlled by three of the registers shown in table 5. the extended registers in bank 1 must first be selected by setting the dv0 bit in reg - ister a to logic 1. the address of the ram location to be accessed must be loaded into the extended ram address registers located at 50h and 51h. the least significant address byte should be written to location 50h, and the most significant bits (right-justified) should be loaded in location 51h. data in the addressed location can be read by performing a read operation from location 53h, or writ - ten to by performing a write operation to location 53h. data in any addressed location can be read or written repeatedly without changing the address in location 50h and 51h. to read or write consecutive extended ram locations, a burst mode feature can be enabled to increment the extended ram address. to enable the burst mode fea - ture, set the bme bit in the extended control register 4ah to logic 1. with burst mode enabled, write the extended ram starting address location to registers 50h and 51h. then read or write the extended ram data from/ to register 53h. the extended ram address locations are automatically incremented on the rising edge of rd or wr only when register 53h is being accessed. see the burst mode timing waveform . ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 24 downloaded from: http:///
extended control registers two extended control registers are provided to supply control and status information for the extended functions offered by the ds17x85/ds17x87. these are designated as extended control registers 4a and 4b, and are locat - ed in register bank 1, locations 04ah and 04bh, respec - tively. the functions of the bits within these registers are described as follows. bit 7: valid ram and time 2 (vrt2). this status bit gives the condition of the auxiliary battery. it is set to logic 1 condition when the external lithium battery is connected to the v baux . if this bit is read as logic 0, the external battery should be replaced.bit 6: increment in progress status (incr). this bit is set to 1 when an increment to the time/date registers is in progress and the alarm checks are being made. incr is set to 1 at 122s before the update cycle starts and is cleared to 0 at the end of each update cycle. bit 5: burst mode enable (bme). the burst mode enable bit allows the extended user ram address regis - ters to automatically increment for consecutive reads and writes. when bme is set to logic 1, the automatic incre - menting is enabled and when bme is set to a logic 0, the automatic incrementing is disabled. bit 3: power active-bar control (pab). when this bit is 0, the pwr pin is in the active low state. when this bit is 1, the pwr pin is in the high-impedance state. the user can write this bit to logic 1 or 0. if either wf and wie = 1 or kf and kse = 1, the pab bit is cleared to 0. bit 2: ram clear flag (rf). this bit is set to logic 1 when a high-to-low transition occurs on the rclr input if rce = 1. writing this bit to logic 0 clears it. this bit can also be written to logic 1 to force an interrupt condition. bit 1: wake-up alarm flag (wf). this bit is set to 1 when a wake-up alarm condition occurs or when the user writes it to 1. wf is cleared by writing it to 0. bit 0: kickstart flag (kf). this bit is set to 1 when a kickstart condition occurs or when the user writes it to 1. this bit is cleared by writing it to logic 0. figure 7. burst mode timing waveform msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt2 incr bme * pab rf wf kf address + 1 as 53h data pw rwl pw rwh data cs ad0-7 ds or r/ w address + 2 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 25 extended control register (4ah) downloaded from: http:///
bit 7: auxiliary battery enable (abe). when written to logic 1, this bit enables the v baux pin for extended functions. bit 6: enable 32.768khz output (e32k). when writ - ten to logic 1, this bit enables the 32.768khz oscillator frequency to be output on the sqw pin. e32k is set to 1 when v cc is powered up. bit 5: crystal select (cs). when cs is set to 0, the oscil - lator is configured for operation with a crystal that has a 6pf specified load capacitance. when cs = 1, the oscilla - tor is configured for a 12.5pf crystal. cs is disabled in the ds17x87 module and should be set to cs = 0. bit 4: ram clear enable (rce). when set to 1, this bit enables a low level on rclr to clear all 114 bytes of user ram. when rce = 0, rclr and the ram clear function are disabled. bit 3: pab reset select (prs). when set to 0, the pwr pin is set high impedance when the ds17x85 goes into power fail. when set to 1, the pwr pin remains active upon entering power fail. bit 2: ram clear interrupt enable (rie). when rie is set to 1, the irq pin is driven low when a ram clear func - tion is completed. bit 1: wake-up alarm interrupt enable (wie). when v cc voltage is absent and wie is set to 1, the pwr pin is driven active low when a wake-up condition occurs, caus - ing the wf bit to be set to 1. when v cc is then applied, the irq pin is also driven low. if wie is set while system power is applied, both irq and pwr are driven low in response to wf being set to 1. when wie is cleared to 0, the wf bit has no effect on the pwr or irq pins. bit 0: kickstart interrupt enable (kse). when v cc volt- age is absent and kse is set to 1, the pwr pin is driven active low when a kickstart condition occurs ( ks pulsed low), causing the kf bit to be set to 1. when v cc is then applied, the irq pin is also driven low. if kse is set to 1 while system power is applied, both irq and pwr are driven low in response to kf being set to 1. when kse is cleared to 0, the kf bit has no effect on the pwr or irq pins. msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 abe e32k cs rce prs rie wie kse ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 26 extended control register (4bh) downloaded from: http:///
system maintenance interrupt (smi) recovery stack an smi recovery register stack is located in the extended register bank, locations 4eh and 4fh. this register stack, shown below, can be used by the bios to recover from an smi occurring during an rtc read or write. the rtc address is latched on the falling edge of the ale signal. each time an rtc address is latched, the register address stack is pushed. the stack is only four registers deep, holding the three previous rtc addresses in addi - tion to the current rtc address being accessed. figure 8 illustrates how the bios could recover the rtc address when an smi occurs. 1) the rtc address is latched. 2) an smi is generated before an rtc read or write occurs. 3) rtc address 0ah is latched and the address from 1 is pushed to the rtc addressC1 stack location. this step is necessary to change the bank select bit, dv0 = 1. 4) rtc address 4eh is latched and the address from 1 is pushed to location 4eh, rtc addressC2 while 0ah is pushed to the rtc addressC1 location. the data in this register, 4eh, is the rtc address lost due to the smi. figure 8. ale waveform rtc addressrtc address-1 4eh rtc address-2 4fh rtc address-3 smi recovery stack 7 6 5 4 3 2 1 0 dv0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 register bit definition 1 2 3 4 ale ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 27 downloaded from: http:///
2423 22 21 20 19 18 17 12 3 4 5 6 7 8 v cc sqwv baux rclr ad0 x2 x1 pwr top view v bat irqks rd ad4 ad3 ad2 ad1 1615 14 13 9 1011 12 gndwr ale cs gnd ad7 ad6 ad5 so, pdip ds17285ds17485 ds17885 v cc sqwv baux rclr ad0 n.c. n.c. pwr n.c.irq ks rd ad4 ad3 ad2 ad1 n.c.wr ale cs gnd ad7 ad6 ad5 edip ds17287ds17487 ds17887 12 3 4 5 6 7 8 9 1011 12 2423 22 21 20 19 18 17 1615 14 13 v baux 2827 26 25 24 23 22 ksrd gnd wr ale cs gnd 21 gnd 20 ad7 19 ad6 18 n.c. 17 ad5 16 ad4 15 ad3 rclr v bat irq v cc v cc pwr x1x2 n.c. ad0ad1 4 12 3 5 6 7 8 9 1011 12 13 14 ad2 sqw tsop ds17285ds17485 ds17885 ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 28 pin conigurations downloaded from: http:///
+ denotes a lead(pb)-free/rohs-compliant package. * a + anywhere on the top mark denotes a lead(pb)-free package. an n or ind denotes an industrial temperature range package. note: a -5 suffix denotes a v cc = 5v10% device, and a -3 suffix denotes a v cc = 3v10% device. part temp range pin-package top mark* ds17285 -3+ 0c to +70c 24 pdip ds17285-3 ds17285-5+ 0c to +70c 24 pdip ds17285-5 ds17285e-3+ 0c to +70c 28 tsop ds17285e3 ds17285e-5+ 0c to +70c 28 tsop ds17285e5 ds17285en-3+ -40c to +85c 28 tsop ds17285e3 ds17285s-3+ 0c to +70c 24 so (300 mils) ds17285s-3 ds17285s-5+ 0c to +70c 24 so (300 mils) ds17285s-5 ds17285sn-3+ -40c to +85c 24 so (300 mils) ds17285sn3 ds17285sn-5+ -40c to +85c 24 so (300 mils) ds17285sn5 ds17287 -3+ 0c to +70c 24 edip ds17287-3 ds17287-5+ 0c to +70c 24 edip ds17287-5 ds17485 -3+ 0c to +70c 24 pdip ds17485-3 ds17485-5+ 0c to +70c 24 pdip ds17485-5 ds17485e-3+ 0c to +70c 28 tsop ds17485e3 ds17485e-5+ 0c to +70c 28 tsop ds17485e5 ds17485s-3+ 0c to +70c 24 so (300 mils) ds17485s-3 ds17485s-5+ 0c to +70nc 24 so (300 mils) ds17485s-5 ds17485sn-5+ -40c to +85c 24 so (300 mils) ds17485sn5 ds17487 -3+ 0c to +70c 24 edip ds17487-3 ds17487-3ind+ -40c to +85c 24 edip ds17487-3 real time ind ds17487-5+ 0c to +70c 24 edip ds17487-5 DS17487-5IND+ -40c to +85c 24 edip ds17487-5 real time ind ds17885 -3+ 0c to +70c 24 pdip ds17885-3 ds17885-5+ 0c to +70c 24 pdip ds17885-5 ds17885e-3+ 0c to +70c 28 tsop ds17885e3 ds17885e-5+ 0c to +70c 28 tsop ds17885e5 ds17885en-3+ -40c to +85c 28 tsop ds17885e3 ds17885s-3+ 0c to +70c 24 so (300 mils) ds17885s-3 ds17885s-5+ 0c to +70c 24 so (300 mils) ds17885s-5 ds17885sn-3+ -40c to +85c 24 so (300 mils) ds17885sn3 ds17887 -3+ 0c to +70c 24 edip ds17887-3 ds17887-3ind+ -40c to +85c 24 edip ds17887-3 real time ind ds17887-5+ 0c to +70c 24 edip ds17887-5 ds17887-5ind+ -40c to +85c 24 edip ds17887-5 real time ind ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 29 ordering information downloaded from: http:///
package theta-ja (c/w) theta-jc (c/w) dip 75 30 so 105 22 package type document no. 24 pdip (600 mils) 21-0044 24 so (300 mils) 21-0042 24 edip (740 mils) 21-0241 28 tsop (465 mils) 21-0273 irq x1 x2 v cc v cc ale ds83c520 ds17285ds17485 ds17885 wr rd cs ad0Cad7 gnd pwr v sb v cc supply control circuit sqw crystal v cc ks rclr v baux v bat ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks www.maximintegrated.com maxim integrated 30 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information substrate connected to ground process: cmos typical operating circuit thermal information downloaded from: http:///
revision number revision date description pages changed 0 4/06 initial release of revised data sheet template 1 4/10 updated the storage temperature ranges, added the lead temperature, and updated the soldering temperature for all packages in the absolute maximum ratings ; removed the leaded parts from the ordering information table; updated the document no. for the package information table. 2, 29, 30 2 5/16 updated package information table 30 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ds17285/ds17287/ds17485/ds17487/ ds17885/ds17887 real-time clocks ? 2016 maxim integrated products, inc. 31 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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